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05-24-2007, 09:24 AM
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#1 (permalink)
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Banned Join Date: Aug 2005 Posts: 3,480
| SSE4 instruction to improve CPU-GPU collaboration Quote:
We already know that Intel's upcoming 45nm processors, code-named Penryn, will harbor a new instruction set called SSE4. The folks at ExtremeTech have now learned some details about an instruction in the SSE4 instruction set that may pave the way for integration between microprocessors and graphics processors. As the site explains, this "streaming load" instruction allows graphics data to bypass the processor's cache: The streaming load instruction is a 16-byte aligned load instruction. But interestingly, the results are held in a temporary stream buffer that bypasses the normal cache hierarchy, a high-priority expressway that other data types haven't received. Intel identified the streaming-load instruction as ideal for GPU-CPU sharing, as well as imaging.
According to the lead architect on Penryn, Stephen Fischer, "This is an interesting instruction, as it opens the door to new areas of collaboration between CPU and the GPU." Fischer adds that the instruction "improves the read buffer from the GPU to the CPU by a factor of eight." ExtremeTech says that, when asked at a lunch panel whether the instruction was a response to AMD's "Fusion" integrated CPU-GPU, Fischer replied, "I could see where people would say that."
| The Tech Report - SSE4 instruction to improve CPU-GPU collaboration Is Intel's 'Penryn' Chip Hiding Graphics Support? |
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05-24-2007, 09:33 AM
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#2 (permalink)
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Self Proclaimed Immortal Join Date: Jan 2006 Location: Denton, TX (UNT) Posts: 2,501
| Re: SSE4 instruction to improve CPU-GPU collaboration Hm...would be kinda interesting considering the power of todays GPUs and if they were not bottlenecked by cache. If this is utilized in the production versions of the chips...we will have even faster clocks and our programs will run that much faster.....seems like its very good technology.
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05-24-2007, 09:37 AM
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#3 (permalink)
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Join Date: Jan 2005 Location: The South Posts: 19,955
| Re: SSE4 instruction to improve CPU-GPU collaboration Quote: |
"I could see where people would say that."
| Who would have thunk it? |
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05-24-2007, 09:46 AM
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#4 (permalink)
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Self Proclaimed Immortal Join Date: Jan 2006 Location: Denton, TX (UNT) Posts: 2,501
| Re: SSE4 instruction to improve CPU-GPU collaboration LOL.....not like intel was cooking this up already though.
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05-24-2007, 10:02 AM
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#5 (permalink)
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Join Date: Jan 2005 Location: The South Posts: 19,955
| Re: SSE4 instruction to improve CPU-GPU collaboration Until Intel get rid of the FSB bottleneck, they will have a problem. Sounds like it is getting better, though. |
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05-24-2007, 10:32 AM
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#6 (permalink)
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Join Date: Jun 2003 Location: Melbourne, Australia Posts: 13,739
| Re: SSE4 instruction to improve CPU-GPU collaboration Quote:
Originally Posted by Trotter Until Intel get rid of the FSB bottleneck, they will have a problem. Sounds like it is getting better, though. | I am thinking HTT 3.0 will go well with graphics cards anyway
But then again, AMD's HTT goes well with anything
__________________ 1 + 1 = 3 if you define 3 as a result of 1 + 1 |
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05-24-2007, 11:23 AM
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#7 (permalink)
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Join Date: Dec 2006 Posts: 19,822
| Re: SSE4 instruction to improve CPU-GPU collaboration Quote:
Originally Posted by Trotter Until Intel get rid of the FSB bottleneck, they will have a problem. Sounds like it is getting better, though. | what FSB bottleneck? Elaborate plz |
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05-24-2007, 12:00 PM
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#8 (permalink)
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Join Date: Jan 2005 Location: The South Posts: 19,955
| Re: SSE4 instruction to improve CPU-GPU collaboration Intel chips do not have on-die memory controllers, so they are limited by the speed of the FSB. Everything must pass through the chipset both ways. This is where AMD really made their speed difference known. Intel keeps raising the FSB, but it is still there.
If Intel has added an on-die mem controller I have not heard about it. |
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05-24-2007, 04:40 PM
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#9 (permalink)
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The Bulldog Join Date: Mar 2006 Location: In an empty Ramen packet Posts: 4,381
| Re: SSE4 instruction to improve CPU-GPU collaboration i agree with trotter. thats their biggest shortcoming. you would think they would have figured that out by now. |
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05-24-2007, 08:29 PM
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#10 (permalink)
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Monster Techie Join Date: May 2007 Location: Australia Posts: 1,508
| Re: SSE4 instruction to improve CPU-GPU collaboration maybe u should tell them |
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