dailytech doesn't know what it's talking about. It thinks Barcelona is K8
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L3-cache – a feat AMD has not taken advantage of since its K6-III+ and K6-2+ processors.
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Actually, the L3 cache for those CPU's was not really designed to be L3 cache.
Back when they were using Socket 7/Super Socket 7, motherboard makers started to put L2 cache on their boards (which is different to CPU's today, which have L1 and L2 cache on-chip)
When K6-2+ came out, AMD decided to put L2 cache on the CPU. the "L3 cache" was actually just the L2 cache on the motherboard, which was superseded by the L2 cache on the CPU.
That is one of the big reasons why the "L3 cache" on those chips didn't really do much.
K10 will have L1, L2 and L3 cache all on the chip, More than that, it will all be on the one die, as well as all four of their cores.
And all four cores will be able to communicate with each other directly.
However, Intel's quad cores have two dies, and can't communicate with each other.
To make matters worse, they actually have to go
through the northbridge to transfer data between dies (on the already restricted FSB).
The high amounts of cache is basically a way to try and compensate for that bottleneck.
It's got what I've mentioned before, including 128-bit FPU's, which can process SSE instructions in a single pass (instead of two, as well as splitting the SSE instruction in half), and one very important thing that dailytech didn't mention, which is a pipeline that can process 4 IPC.
Things like the prefetcher, 512 entry branch predictor, and virtualisation are just icing on the cake.
AMD Unveils "Barcelona" Architecture 
Re: AMD Unveils "Barcelona" Architecture 
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